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The 65C02 core

A processor emulator is judged on evidence: here, 2.54 million cases compared with a public reference.

One bus access per cycle

The core (src/cpu/cpu65c02.c) runs an instruction by reproducing the sequence of bus accesses, one per cycle, with the dummy reads the real processor makes. That is what makes the cycle count exact, hence time.

The oracle

The core is compared with SingleStepTests (the wdc65c02 set): 254 opcodes × 10,000 cases = 2,540,000 cases. For each, the final state, the RAM, the cycle count and the exact sequence of bus accesses are compared. The required score is 100%, and make test-oracle fails below it. A quick version (test-oracle-quick) is used day to day.

What the oracle does not say

Phosphoneo writes it down in accuracy rather than hiding it:

  • the oracle’s cb.json and db.json files (WAI and STP) are empty: their behaviour follows the manufacturer’s datasheet, unmeasured;
  • interrupts and RESET are not covered by the oracle (dedicated tests, test-irq, check the functional behaviour);
  • for $5C, the oracle gives 4 cycles where the datasheet says 8: the oracle is followed, the gap is not settled on silicon;
  • the “decimal” cycle of immediate ADC/SBC reads $007F or $0000 as the oracle gives it, without the datasheet explaining it.

Sources in the repository : docs/ACCURACY.md, docs/ARCHITECTURE.md.